Historically, the feature size of a chips was the length of the silicon channel between source and drain in field effect transistors (FET). Today, the feature size is typically the smallest element in the transistor.

The best chips today have a 3nm feature. TSMC N3 risk production is scheduled in 2021. The volume production is targeted in second half of 2022

TSMC is expected to enter 2 nm risk production around 2023.

Intel's 2019 roadmap scheduled potentially equivalent 3 nm and 2 nm nodes for 2025 and 2027 respectively. In December 2019, Intel announced plans for 1.4 nm production in 2029.

In August 2020, TSMC began building a R&D lab for 2 nm technology in Hsinchu, expected to become partially operational by 2021. In September 2020, TSMC Chairman Mark Liu said they would build a plant for the 2 nm node at Hsinchu in Taiwan, and might install production at Taichung dependent on demand.