They can coat an entire 4-inch wafer with a uniform array of highly aligned carbon nanotubes in 40 seconds.
A purification process produces nanotubes in solvents, or nanotube inks, which they then flow at a constant velocity and thickness over a layer of water. At the interface between the ink and water, the nanotubes begin to concentrate and self-organize, forming a liquid crystal. That liquid crystal is then transferred on a substrate moved through the ink and water interface. The result is a wafer covered in trillions of highly aligned carbon nanotubes.
The nanotube density is near that needed for electronics. They determined the alignment of the tubes to be within 6° locally. This almost ideal nanotube ordering led to excellent electrical properties that were confirmed consistent across the entire wafer.
The process is a big advance for carbon nanotube research. However, it does need some tweaks before nanotube computer processors end up in smartphones and laptops. The industry standard is 12-inch wafers, so the process, patented through the Wisconsin Alumni Research Foundation, needs to be scaled up while maintaining the uniformity of the nanotube alignment.
They can also be deposited in multiple layers, like 3D integrated circuits. That would allow us to increase the number of transistors significantly.