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IPFS News Link • Robots and Artificial Intelligence

Future Wafer Scale Chips Could Have 100 Trillion Transistors

•, by Brian Wang

They had 0.86 PetaFLOPS of performance on the single wafer system. The waferchip was built on a 16 nanomber FF process.

The WSE is the largest chip ever built. It is 46,225 square millimeters and contains 1.2 Trillion transistors and 400,000 AI optimized compute cores. The memory architecture ensures each of these cores operates at maximum efficiency. It provides 18 gigabytes of fast, on-chip memory distributed among the cores in a single-level memory hierarchy one clock cycle away from each core. AI-optimized, local memory fed cores are linked by the Swarm fabric, a fine-grained, all-hardware, high bandwidth, low latency mesh-connected fabric.

Wafer-scale chips were a goal of computer great Gene Amdahl decades ago. The issues preventing wafer-scale chips have now been overcome.

In an interview with Ark Invest, the Cerebras CEO talks about how they will beat Nvidia to make the processor for AI. The Nvidia GPU clusters take four months to set up to start work. The Cerebras can start being used in ten minutes. Each GPU needs two regular Intel chips to be usable.

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